1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which allows the adjustment of the operating speed of a circuit or a semiconductor device constituting the circuit and the adjustment of the consumption of electricity, wherein the circuit includes one or more circuits, such as MOSIC (Metal Oxide Semiconductor Integrated Circuit).
2. Description of Related Art
FIGS. 1A and 1B is a circuit diagram of a known inverter using a P-channel MOS transistor and an N-channel MOS transistor both in which a well potential (or substrate potential) is predetermined. The reference numerals T11 and T13 designate the P-channel MOS transistors and the reference numerals T12 and T14 designate the N-channel MOS transistors, respectively. There are two sets of series connected transistors: T11 with T12 and T13 with T14. T11 and T13 connected in series T12 and T14 are connection in series, and the junctions therebetween is connected to an output terminal Out.
The source of the P-channel MOS transistor T11 is delivered with a source voltage Vcc, and the source of the N-channel MOS transistor T12 is grounded, and the gate of each transistor T11 aid T12 is connected to a voltage source of signals (not shown) in FIG. 1A.
The N-well of the P-channel MOS transistor T11 shown in FIG. 1A is delivered with a source voltage Vcc as the source thereof is, and the P-well of the N-channel MOS transistor T12 is at the ground potential as the source thereof is. These potentials are predetermined.
The N-well of the P-channel MOS transistor T13 and the P-channel of the N-channel MOS transistor T14 shown in FIG. 1B are also at a predetermined potential.
There is also known a MOSIC designed to change a threshold voltage of a transistor in accordance with the operating conditions of the circuit which is disclosed in "ISSCC 95, Feb. 17, 1995, p. 318-319/FP19.4 (50% Active Power Saving without Speed Degradation Using Standby Power Reduction (SPR) Circuit)".
In this MOSIC the well potential is selectively switched over between two bits depending upon the circuit being in operation or not in operation.
In general, when the potential of a well or substrate is predetermined in a transistor constituting the MOSIC, the threshold voltage of the transistor is automatically fixed, thereby leaving no room for controlling the operating speed of the circuit or transistor and the consumption of electricity.
In the case of an expedient for varying the well potential by two stages, it is difficult to effect the subtle control of the operating speed and consumption of electricity.
There are MOSICs which include a circuit capable of predetermining an operating frequency as desired or a circuit operable at a plurality of source voltages. In neither case the well potential or substrate potential can be varied in accordance with the operating frequency or source voltage. As a result, the following problems arise:
In the former case, a variation in the operating frequency changes a time required for completing a predetermined operation of the circuit; for example, when a circuit in the MOSIC is operated at a high frequency, the transistor constituting the circuit is required to operate at a high speed, whereas if it is operated at a low frequency, the transistor may be operated at a low speed. When the circuit is designed to operate at a high frequency, the transistor must be unnecessarily operated at a high speed.
In the latter case, when the circuit is used at a high source voltage, the transistor is operated at a high speed, and the consumption of electricity becomes large. In contrast, when the circuit is used at a low source voltage, the consumption of electricity is reduced but the disadvantage is that the operating speed of the transistor becomes low.